- Floor Planning, Placement, Timing Closure, Synthesis, STA, Formal Verification, Low Power Checking (CLP/MVRC)
- Should have worked on 28 nm
- Expertise in Cadence/Synopsys flows.
- RTL coding, Verification and FPGA prototyping...
Expertise in RTL, Logic design
Experience inRTL Design
Good hands on experience in Logic design
Experience of Micro Architecture preparation
Coding Experience in Verilog, System Verilog HDL languages
Experienced in Developing Environments for Li...