Physical Design

xyz fashion

Experience : 3 to 10 Yrs.

Max CTC: 18LPA

PAN India to Bangalore

Notice Period: Immediate.

Roles & Responsibilities would be:

Should have experience in handling full chip activities, leading a full chip physical design team

Job function: Design planning, partition, full chip level floorplan, bump placement, bump routing, power routing,

block level floorplan, power plan, place and route, CTS, STA, physical verification, DRC, LVS, IR-EM analysis,

debugging gds level issues, giving technical guidance to junior engineers in block/full chip level activities.

Experience : 3 - 10 Years

No. of Openings : 4

Education : Professional Degree

Role : Physical Design

Industry Type : Engineering / Cement / Metals

Gender : [ Male / Female ]

Job Country : India