Overview
Looking for a Senior Engineer with 3-7 years of experience in digital design verification domain.
Technical Know-How Needed
- Good hands-on experience of System Verilog & uVM (Universal Verification Methodology)
- Capable of developing testbench architecture from scratch using uVM methodology, Writing tests, collecting coverage, Register verification using uVM RAL
- C/C++ based Verification
- Writing Assertions, Performing Formal verification
- Power Aware Verification to check design in different low power modes
Knowledge of following will be an added advantage
- Good Understanding of ARM M0/M4 core, Interconnect, AHB, APB, and other ARM peripherals
- Know-how of DSP; DMA controller ; Serial Interfaces like I2C, SPI, I2S
All the best! - 
