-Support project implementation SAP.
-Involved in both SIT and UAT during implementation and update HPQC.
-Capture all exceptional requirements.
-Have exposure towards preparing process map and SOP for order to cash process.
-ARIS mapping creatio...
Dst Project In School Of Electronics Engineering, Vit University, Chennai
Project Title : Development Of A Spice-Compatible Model For Single Event Transients For Circuit Simulations And Its Application In Set-Tolerant Dll Design.
Key Skills : r&d scientist,junior research fellow,senior research fellow