RS 5,00,000 To 13,00,000 Bangalore
• Develop micro-architecture and RTL implementation. • Block level/ full chip integration and design. • Hands-on with Lint, CDC , LEC and preferably Low Power check tools • Some experience of AXI/AHB • design in System Verilog and timin...
Key Skills : ASIC Synthesis,ASIC Design,lint,cdc,Synthesis,Verilog,ovm,uvm,RTL,Verification Engineer,RTL design