• RTL Design and verification Engineer


    1. 3 - 7 yrs
    2. Bangalore NA NA NA
    Rs 5,00,000 to 13,00,000 p.a.

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  • Job View 438 Views
  • Applicants Less than 5 Applicants
  • 2017-03-19

Job Description

Develop micro-architecture and RTL implementation.

Block level/ full chip integration and design.

Hands-on with Lint, CDC , LEC and preferably Low Power check tools

Some experience of AXI/AHB

design in System Verilog and timing, performance & power optimizations

Work with functional verification team to review test plans and coverage

Good understanding of design implementation flows and tools (Synthesis, STA, and DFT)

Good knowledge of configuration tools and workflow tools: Clearcase/ClearQuest, etc.

Hands on project experience with leading edge verification methodologies like OVM/UVM

Hands on project experience in coverage/assertion driven verification

Advanced skills in various programming languages including Verilog, System Verilog, C, C++, PERL, TCL

Key Skills


Export - Import / Trading

Functional Area

Engineering/ Engineering Design / R&D / Quality

Number of Vacancy



B.Tech/B.E, M.Sc, M.Tech, Ph.D/Doctorate, MPHIL

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