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  • Job View 282 Views
  • Applicants Less than 5 Applicants
  • 2017-06-02

Job Description

Will Be Responsible For Designing And Implementing Dft Techniques (Memory Bist/Scan /On-Chip Compression/At-Speed Scan/Test-Clocking/Boundary Scan/Analog Testing/Pin-Muxing/Logic Bist) On Complex Socs To Improve Testability

Test Modes Implementation And Verification, Scan Insertion Including On-Chip Compression

Implementing, Integrating And Verifying Memory Bist And Boundary Scan

Test Vector (Stuck-At/At-Speed/Path Delay/Sdd/Iddq/Bridging Fault) Generation With High Test Coverage And Simulations At Gate Level With Timing (Sdf)

Closing Working With Test Engineer And Product Engineer Team To Understand Testability Requirement For Zero-Defect

Post-Silicon Bring-Up Support

Basic Understanding Of Complete Soc Design And Flow

Cross Functional Teams Interaction For Issue Resolution

Participate In Driving New Dft Methodology And Solutions To Improve Quality, Reliability And In-System Test And Debug Capability

Mentoring New Team Members

Key Skills


Consumer Durables / Home appliance

Functional Area

Engineering/ Engineering Design / R&D / Quality

Number of Vacancy




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