Expertise in Rtl Verification
- Verification of Rtl Using Sv, Ovm/uvm
- Experience in Verification Environment Development
- Verification of Gate Level Netlist Using Ovm/uvm Testbenches
- Expertise in Standard Protocols
- Experience in Automat...
- Engineer Will Be Responsible for Designing the Asic to Meet the Specifications Defined.
- Responsible for Defining and Implementing Micro-architecture Design and Development of Various Functional Blocks.
- Responsible for Design of Soc-level Log...
Key Skills : soc design,asic design,rtl design,dft system verilog,digital designer,digital artist
1.Expertise in ASIC/SoC verification using HVLs. Knowledge of networking protocols will be an added advantage.
2.Expertise in SystemVerilog, Verification Methodologies such as OVM,UVM,etc.
3.Should have worked on at least one full-chip or module-le...
- Expertise in Low PowerPhysical design and Static Timing Analysis.
- Experience in Netlist-GDS flow which includes Synthesis, Layout(Floorplan, Place and Route, CTS (clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Ver...
Job Responsibility Involves Full Ownership of Complete Memory Development Process Starting from Freezing of Specifications , Forming the Verification Plan , Ensuring the Timely Approvals from Customer , Self Execution of Memory Design , Verification.
-The selected intern candidate will be part of the IP verification/ VIP team in Group, smartchip design , India and be based at Bangalore.
-The focus area of activities would be Verification/ VIP/ Test Environment devel...
RS90,000 To 1,25,000Haridwar, Kashipur, Rudrapur-Udham, Sitarganj
Hiring for urgent opening for Electronics and Electrical Engineers.
Skills Required: Production, Quality, maintenance, PLC, e-CAD, SCADA, VLSI Design,
Candidate should be flexible to work in different domains.
Functional Area: Production, Manu...
- Experience : 8 - 12 Years
- Location : Bangalore
- 8+ Years of experience in ASIC Verification
- Expert in System Verilog and verification methodologies
- Expertise in Bus protocols
- Experience with simulators, debug tools, and commercial v...
- Expertise in Low PowerPhysical design and Static Timing Analysis
- Experience in Netlist-GDS flow which includes Synthesis, Layout(Floorplan, Place and Route, CTS (clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verifi...
Interview Date: 12th July 2016 – 19th July 2016
Interview Timing: 10 am to 5 pm
Working Nature: Full Time
Qualification: BE (CSE, IT, EEE, ECE), MCA, M.Sc (CS, IT)
Job Location: Erode
• Develop micro-architecture and RTL implementation.
• Block level/ full chip integration and design.
• Hands-on with Lint, CDC , LEC and preferably Low Power check tools
• Some experience of AXI/AHB
• design in System Verilog and timin...
- Minimum 4 years of experience in Design Verification
- Working experience in IP / SoC verification
- Should have the expertise to develop block level / system level verification environments using System Verilog and UVM / OVM
- Experience to de...
DV Engineers having experience in (System Verilog, UVM)
Experience 3 Years to 8 Years
Job Locations Bangalore, Shanghai,
a ) SoC based verification:
- Must have working knowledge of Verilog , System Verilog (HVL)
Key Skills : system verilog,uvm,ovm,axi,ace,ahb,apb,verilog,amba,data collection,data analyst,data...
RS1,75,000 To 4,50,000North Delhi, South Delhi, East Delhi, West Delhi
As An Application Engineer You Will Work Directly, Sometimes in Great Depth, with Customers to Understand Their Technical and Business Challenges and Help Them Appreciate How to Apply Our Products Toward the Resolution of Their Problems.
This is Vaibhav from SSJ Solutions and we have some exciting career options for you.
We have been providing exciting career options at senior/middle levels (from CEOs, SBU Heads down to PMs/PLs) since 1991 in IT/Software, Telecom, Finance, HRD for I...
Expertise in Low PowerPhysical design and Static Timing Analysis
Experience in Netlist-GDS flow which includes Synthesis, Layout(Floorplan, Place and Route, CTS (clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verificat...
N Depth Knowledge Of System Verilog And Verification Methodologies Like Ovm, Uvm
·Working Experience On The Uart, Pcie, Avalon Interface, Axi, Fpga Environment
·Working Knowledge Of Modern Pc Architecture; Specific Io Architecture Knowledge A...
Key Skills : good knowledge on functional and code coverage,perform the overall verification methodology using hvls like system verilog,ovm,uvm,extensive...
VLSI Design Engineers has a training program for 6 - 9 months and work in Design, Modeling, Verification, FPGA Validation, and Product Validation for IPs, FPGAs, ASICs and SOCs as well as EDA Products working in areas of Verilog, SystemVerilog and V...
RS5,00,000 To 50,00,000Tirupati, Barpathar, Dibrugarh, Chandigarh, Sector 47 Chandigarh, Betul-Goa, Panaji, Bangalore, Jirapur, Ujjain, Mumbai, Mumbai Suburb, Pune
- Test the Product Again After Initial Mass Production to Ensure that Any Fabrication Faults are Uncovered Prior to Release and Shipping.
- Prepare Detailed Specifications and Methods to Interface Computer Products -the Interaction Between Cpu and P...