RS 5,00,000 To 13,00,000 Bangalore
• Develop micro-architecture and RTL implementation. • Block level/ full chip integration and design. • Hands-on with Lint, CDC , LEC and preferably Low Power check tools • Some experience of AXI/AHB • design in System Verilog and timin...
Key Skills : asic synthesis,asic design,lint,cdc,synthesis,verilog,ovm,uvm,rtl,verification engineer,rtl design,system...
RS 1,75,000 To 2,25,000 Bangalore
Job Description: - Managing & Processing Samples for Analysis. - Handling of Analytical Instruments for the Analysis of Samples. - Preparing Reports & Documentation of Records.
Key Skills : r&d associate,r&d engineer,r&d executive
Mirafra Technology Pvt Ltd
RS 3,00,000 To 4,00,000 Bangalore
Should be very strong in Synthesis & Timing concepts - Should have knowledge of DC-topo, RTL Compiler or talus - Should have handled both block and top level. - Should have done both pre and post layout STA
Key Skills : synthesis engineer,synthesis engineering