Should be very strong in Synthesis & Timing concepts
- Should have knowledge of DC-topo, RTL Compiler or talus
- Should have handled both block and top level.
- Should have done both pre and post layout STA
• Develop micro-architecture and RTL implementation.
• Block level/ full chip integration and design.
• Hands-on with Lint, CDC , LEC and preferably Low Power check tools
• Some experience of AXI/AHB
• design in System Verilog and timin...