Clipocruit Job Placements & Career Counseeling Pvt Ltd
RS6,00,000 To 16,00,000Hyderabad
• Analog and Mix signal block connectivity verification at RTL and gate level.
• Integrate analog models with RTL and GATE simulation environment.
• Define test strategy for Analog blocks - create test plan, define test concurr...
- Engineer Will Be Responsible for Designing the Asic to Meet the Specifications Defined.
- Responsible for Defining and Implementing Micro-architecture Design and Development of Various Functional Blocks.
- Responsible for Design of Soc-level Log...
Key Skills : soc design,asic design,rtl design,dft system verilog,digital designer,digital artist
VLSI Design Engineers has a training program for 6 - 9 months and work in Design, Modeling, Verification, FPGA Validation, and Product Validation for IPs, FPGAs, ASICs and SOCs as well as EDA Products working in areas of Verilog, SystemVerilog and V...
• Develop micro-architecture and RTL implementation.
• Block level/ full chip integration and design.
• Hands-on with Lint, CDC , LEC and preferably Low Power check tools
• Some experience of AXI/AHB
• design in System Verilog and timin...
Expertise in RTL Verification
* Verification of RTL using SV, OVM/UVM
* Experience in verification environment development
* Verification of gate level netlist using OVM/UVM testbenches
* Expertise in standard protocols
* Experience in...
Technology Domain: Pega Intelligence Process and Use Case Managment Platform
lead System Architect
-drives Scope Definition Workshops and Owns Delivery of the Completed Overall Responsibility for the Design and Technical Delivery
Key Skills : architect,technical system architect,deployment engineer,system architect,senior system architect,lead system architect,deployment...