RS7,00,000 To 20,00,000Ahmedabad, Bangalore, Noida
Candidate Will Be Involved In Developing Testbench For The Block / Cluster, Testcases, Tesplans And Functional And Code Coverage Closure Activities And Reviews Of Documents And Code.
Candidate Will Be Individually Responsible For Successful Delive...
Job Responsibility Involves Full Ownership of Complete Memory Development Process Starting from Freezing of Specifications , Forming the Verification Plan , Ensuring the Timely Approvals from Customer , Self Execution of Memory Design , Verification.
-The selected intern candidate will be part of the IP verification/ VIP team in Group, smartchip design , India and be based at Bangalore.
-The focus area of activities would be Verification/ VIP/ Test Environment devel...
• Develop micro-architecture and RTL implementation.
• Block level/ full chip integration and design.
• Hands-on with Lint, CDC , LEC and preferably Low Power check tools
• Some experience of AXI/AHB
• design in System Verilog and timin...
1.Expertise in ASIC/SoC verification using HVLs. Knowledge of networking protocols will be an added advantage.
2.Expertise in SystemVerilog, Verification Methodologies such as OVM,UVM,etc.
3.Should have worked on at least one full-chip or module-le...
DV Engineers having experience in (System Verilog, UVM)
Experience 3 Years to 8 Years
Job Locations Bangalore, Shanghai,
a ) SoC based verification:
- Must have working knowledge of Verilog , System Verilog (HVL)
Key Skills : system verilog,uvm,ovm,axi,ace,ahb,apb,verilog,amba,data collection,data analyst,data...
Clipocruit Job Placements & Career Counseeling Pvt Ltd
RS6,00,000 To 16,00,000Hyderabad
• Analog and Mix signal block connectivity verification at RTL and gate level.
• Integrate analog models with RTL and GATE simulation environment.
• Define test strategy for Analog blocks - create test plan, define test concurr...