ASIC Design Jobs in Hyderabad

Design & Verification Sr. Engineer/Lead/Managers – ASIC (Design Verification )

Tessolve Semiconductor

uvmsystem verilogsocippciemipizebudesign & verification engineer

VLSI Design Engineer

AdvanSoft

  • Experience 5 - 9 yrs
  • Salary Rs.15.0 - 40.0 Lakh/Yr
  • Location Hyderabad
c languagevlsi-very large scale integrationedasystem verilogasic verificationrtlglsuvmvlsic

Design Verification

APAQ Technologies Pvt Ltd

design verificationasic design verification engineerverilogsystem verilogpcie
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